IEEE 1296-1987

IEEE 1296-1987 IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II
standard by IEEE, 08/03/1988

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Full Description

Scope

This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.(1) This standard defines a high-performance 32-bit synchronous bus standard.(2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.(3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.(4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.(5) Options within the standard will be clearly identified.(6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.(7) The standard is intended to support heterogeneous processor types in the same system.(8) Message passing format and protocol is intended for future migration to a serial system bus.

Abstract

New IEEE Standard - Inactive-Withdrawn.This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.