Full Description

Scope

This is a full-use standard, a revision of ISO/IEC 13213:1994; its scope reflects accumulated experience with the CSR architecture since it was first promulgated as a standard in 1991. In the intervening years, two bus standards, Scaleable Coherent Interface (SCI), IEEE Std 1596-199x, and Serial Bus, IEEE Std 1394-1995, have been the source of most practical implementation experience. The revised scope of the CSR architecture is given below: a) The overall architectural framework partitions the total available address space into equal spaces available to individual nodes. A node's address space is in turn partitioned into regions which have different usage models, e.g., memory space, private space for vendor uses, configuration ROM and an I/O space (units space) where transactions may have side effects; b) A minimal transaction set (read, write and lock requests and their associated completion responses) required for compliant bus standards. Bus bridges compliant with this architecture, whether in a homogeneous or heterogeneous environment, are also expected to transport this transaction set; c) Fundamental control and status registers (CSRs) are defined to provide a common infrastructure for all compliant buses. In some cases the details of the registers are entirely bus-dependent but the function is common to all compliant buses; d) Message request and response CSRs are specified to enable directed delivery or broadcast of messages to multiple nodes. The message format permits organizations or vendors to define the meaning of the data payload without the need for a centralized registry of all possible formats; and e) Configuration ROM provides self-descriptive data structures that permit nodes to uniformly characterize the device services available. This is critical for buses that permit live insertion and removal of nodes; each newly inserted node contains sufficient information for it to be uniquely identified and for the requisite device drivers to be loaded. Although the original CSR architecture anticipated widespread development of bridges between heterogeneous bus standards and a diversity of addressing modes, both fixed and variable, no such implementations have been made. As a consequence, the most significant changes in scope between the earlier CSR architecture and this standard are the adoption of a single, fixed addressing model and the removal of tutorial material pertaining to the design of bridges.

Purpose

The cardinal purpose of any revised standard is to correct or resolve ambiguities or deficiencies in the prior standard that have been revealed by applications (or attempted applications) of the earlier standard. This standard also preserves the following objectives of the original standard: a) Scalability. The CSR architecture is intended to be applicable to a wide range of bus standards and furthermore to a wide range of device capabilities implemented by particular products; b) Extensibility. The architecture supports contemporary processor and bus designs and, to the extent that one can anticipate the future, should be a useful framework for similar new designs. In particular, the addressing model is well suited to 32-bit and 64-bit processors. The CSR architecture creates no obstacles for the designers of adapters that bridge between common system memory and I/O buses; c) Open systems interoperability. The configuration ROM data structures, as well as the fundamental CSRs, provide tools which vendors may use to guarantee that their devices will work with each other. The segregation of one unit architecture from another tends to restrict possible adverse affects by one module, node or unit upon another; d) Manageability. The CSR architecture permits the design of systems that require little or no administration and are simple to support. Automatic configuration based upon configuration ROM is a key feature; indeed, it is essential when the applicable bus standard supports live insertion and removal of devices; and e) Parallelism. Although not directly addressed by this standard, the architecture contains no features that might preclude its use in a multiprocessor configuration. The above is a smaller set of objectives than described in ISO/IEC 13213:1994. The working group responsible for the development of this revised standard believes that its usefulness has been enhanced by restricting some of the unrealized goals of the earlier work.

Abstract

Revision Standard - Inactive-Withdrawn.Administratively withdrawn January 2007 A common bus architecture (which includes functional components--modules, nodes,and units--and their address space, transaction set, CSRs, and configuration information) suitablefor both parallel and serial buses is provided in this standard. Bus bridges are enabled by the archi-tecture, but their details are beyond its scope. Configuration information is self- administered byvendors and organizations based upon IEEE Registration Authority company_id.

Product Details

Published: 09/06/2002 ISBN(s): 0738131108, 9780738131009 Number of Pages: 77File Size: 1 file , 570 KB Product Code(s): STDWD94977